1. Field of the Invention
The present invention relates generally to digital device interfaces, and more specifically to low pin count interfaces to interconnect USB devices on a circuit board.
2. Description of the Related Art
The Universal Serial Bus (USB) allows coupling of peripheral devices to a computer system. USB is a serial cable bus for data exchange between a host computer and a wide range of simultaneously accessible devices. The bus allows peripherals to be attached, configured, used, and detached while the host is in operation. For example, USB printers, scanners, digital cameras, storage devices, card readers, etc. may communicate with a host computer system over USB. USB based systems may require that a USB host controller be present in the host system, and that the operating system (OS) of the host system support USB and USB Mass Storage Class Devices.
USB devices may communicate over the USB bus at low-speed (LS), full-speed (FS), or high-speed (HS). A connection between the USB device and the host may be established via digital interconnect such as Interchip USB, ULPI, UTMI, etc., or via a four wire interface that includes a power line, a ground line, and a pair of data lines D+ and D−. When a USB device connects to the host, the USB device may first pull a D+ line high (the D− line if the device is a low speed device) using a pull up resistor on the D+ line. The host may respond by resetting the USB device. If the USB device is a high-speed USB device, the USB device may “chirp” by driving the D− line high during the reset. The host may respond to the “chirp” by alternately driving the D+ and D− lines high. The USB device may then electronically remove the pull up resistor and continue communicating at high speed. When disconnecting, full-speed devices may remove the pull up resistor from the D+ line (i.e., “tri-state” the line), while high-speed USB devices may tri-state both the D+ and D− lines.
Embedded and portable products are often implemented with a USB interface because of their popularity, driver support, interoperability and relative low cost of USB devices. However, standard USB devices include an analog physical layer (PHY) component, along with pull-up and pull-down resistors that constantly consume power (even when in suspend or standby). These aspects of USB make it less attractive to power conscious embedded devices, particularly those operating from a battery. It has therefore become desirable to provide USB connectivity, without the added power consumption of analog PHYs and pull-up and pull-down resistors.
The USB-IF (USB Implementers Forum) created and released an Interchip 1.0 specification addressing some of the analog PHY issues of USB, and is therefore more attractive for portable devices, but the interface is not capable of HS (high speed) USB transfer speeds, and retains the differential data (D+/D−) aspect of USB, which typically requires eye diagrams, clock recovery and synchronization. This increases the complexity of the implementation over a straightforward digital clock and data interface, and limits the transmission length to 10 cm or less. It also makes it very difficult to carry this scheme to 480 Mb/s performance.
Various interface solutions have been implemented and proposed in the past. For example, U.S. Pat. No. 4,785,396 defines use of Manchester encoding over differential data lines. This requires clock recovery and is very similar to Interchip USB in terms of its limitations. It is also constructed to connect multiple devices together, instead of the point-to-point structure inherent to USB. It uses pull-ups to indicate idle state, and uses other “static” states to indicate collision detection and valid data. It doesn't have the ability to communicate USB Reset, or USB Resume without an intervening protocol, which would unnecessarily burden the implementation. Also, the defined arbitration mechanism can be deemed unnecessary since it is already defined in USB upper level protocol.
U.S. Pat. No. 5,7903,993 defines a separate interrupt line to allow “slave” devices to operate on a bus with the single master. It also defines a command sequence, which is a packet protocol that would essentially act as a header to all USB traffic, or would need to be used to transmit control information such as a USB Reset. This would not work well in a USB environment without substantial modification to the USB Device itself.
U.S. Pat. No. 4,847,867 defines use of a bidirectional data line, but the master sources the clock at all times. The protocol uses the rising edge of the clock to send and the falling edge to receive data.
U.S. Pat. No. 6,073,186 defines use of a bidirectional data line, but the master sources the clock at all times. This would not provide a robust solution with a dual data rate scheme over longer circuit trace lengths. It would therefore not be viable for certain applications. Also, no provision is made for static signaling such as USB Reset and Resume.
U.S. Pat. No. 7,003,585 B2 defines use of a transceiver scheme for clock extraction, and defines a transport protocol for the interface that is redundant in a USB environment.
This is not a digital replacement serial bus for USB, and would therefore not meet the requirements for a portable device. It is designed mainly for long cable runs (an example of 75' is given in the background section).
U.S. Pat. No. 5,970,096 describes a bus structure between one master and one or many slave devices. It describes an idle condition using the static condition of the interface, but no provision is made for USB Reset or Resume through static states on the bus.
US Patent Application US 2002/0095541 A1 describes an analog serial data transfer scheme and doesn't apply to digital serial transfers.
US Patent Application US 2004/0263321 A1 describes a serial data transmission system that can also supply power from a transmission source to a receiver. It focuses on power delivery and doesn't provide static states for USB Reset or USB Resume. It also wouldn't map successfully to a simple two-wire scheme to replace standard USB.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.